Automated hot-spot fixing system applied to the metal layers of 65-nm logic devices
Hot-spot clearance using process simulation is indispensable for low-k1 lithography processes. Hot spots will occur mainly depending on local pattern context. Appropriate calibration of design rules, ...
Complementary dose and geometrical solutions for electron beam direct write lithography proximity effects correction: application for sub-45-nm node product manufacturing
After the successful results obtained in the last few years, electron beam direct write (EBDW) lithography for use in integrated circuit manufacturing has now been demonstrated. However, throughput an...
Kim Yaw Tong and Thiago Hersan Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, Pennsylvania 15213
Davide Pandini ST Microelectronics, via Olivetti 2, Agrate Brianza, 20041, Italy
In the past, complyingwith design rules was sufficient to ensure acceptable yields fora design. However, for sub-100-nm designs, this approach tends tocreate patterns that cannot be reliably printed for a givenoptical setup, thus leading to hot spots and systematic yieldfailures. Recent challenges faced by both the design and processcommunities call for a paradigm shift whereby circuits are constructedfrom a small set of lithography-friendly patterns that have previouslybeen extensively characterized and ensured to print reliably. We describethe use of a regular design fabric for defining theunderlying layout geometries of the circuit. While the direct applicationof this methodology to the current application-specific integrated circuit (ASIC)design flow would result in unnecessary area and performance penalties,we overcome these penalties via a unique design flow thatensures shape-level regularity by reducing the number of required logicfunctions as much as possible as part of the top-downdesign flow. We show that with a small set ofBoolean functions and careful selection of lithography-friendly patterns, we notonly mitigate but essentially eliminate such penalties. Additionally, we discussthe benefits of using extremely regular designs constructed from alimited set of lithography-friendly patterns not only to improve manufacturabilitybut also to relax the pessimistic constraints defined by designrules. Specifically, we introduce the basis to exploit the regularityin the layout patterns by using “pushed-rules” for logic design,as is commonly done for static random access memory (SRAM).This in turn facilitates a common optical proximity correction (OPC)methodology for logic and SRAM. Moreover, by taking advantage ofthis newfound manufacturability and predictability of regular circuits, we showthat the performance of logic built on regular fabrics cansurpass that of seemingly more arbitrarily constructed logic.
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